SiLogy: Shaping the Future of Collaborative Chip Design Verification

Microchips have become miracles of human invention, managing billions of transistors on the same silicon chip to process information. 

However, developing a microchip is a laborious undertaking. Not only is designing a new microchip a tough computational problem, but engineers also need to verify the design and ensure the chip works as expected, securely, and performantly. Companies developing microchips employ large teams of design verification teams and DevOps teams to host a myriad of tools needed for the verification process. 

Founded by Kay Li and Paul Kim in 2023, and going through the Y Combinator Winter 2024 batch, SiLogy provides a web platform to empower chip developers and verification engineers to verify chip designs in minutes. It integrates various design verification tools into a single platform, saving companies the hassle of hosting them themselves, and helping them bring chips faster to market.

Learn more about the future of collaborative chip design verification from our interview with the co-founder and CEO, Kay Li:

Why Did You Start SiLogy?

Like many entrepreneurs, I couldn’t see myself on a corporate career path, having to impress the right people to get ahead. So, instead, I chose the startup path, exploring with my co-founder Paul how we could build a modern web platform to simulate and debug chip designs. 

It’s a pain point I had experienced before when I was working as a software engineer at Hudson River Trading, where we designed and verified our own custom chips. Having experience with C++ and FPGAs, I was responsible for testing a number of chips used in trading and at the end worked on the testing infrastructure, making sure we could run as many tests as fast as possible.

From this experience, I knew that chip developers spend about 70% of their time on verification rather than designing and optimizing a new chip. There’s an increasing productivity gap between the chip designers and the verification engineers who ensure the chip works as expected. Maybe we could do something about it. I checked in with Paul, who had been my roommate in college, and we’ve been friends ever since. Coming from backend development at Cloudflare, he was looking for something new and exciting to do, which led us both to apply to Y Combinator and found SiLogy as a startup. 

How Do You Make Chip Design Verification Collaborative?

It’s difficult to verify new chip designs. In each clock cycle, millions of things happen simultaneously as transistors change state to calculate results and retrieve or store information. So, the state space of what a chip could do in a clock cycle is giant, and the amount of testing you need to do increases tremendously with the size of the chip. 

As CPUs and GPUs get more cores and chipmakers develop custom silicon chips or large systems-on-chip (SoCs), e.g., packaging CPUs and GPUs on one chip, the amount of testing required increased even more. When COVID-19 triggered a global chip shortage, people were surprised at how ubiquitous chips have become, going into cars, smart IoT devices, or trading systems—practically everywhere. 

Every company does chip verification a bit differently, but generally, they need to use many different tools and have large DevOps teams to manage them all. We have created one single platform to integrate all of them together. With our CI/CD tool, you can run many tests in parallel and keep track of all the tests you ran in the past. We’re also visualizing the results of what’s going on in the chip. 

Our goal right now is to streamline the workflow for chip developers even further so they can see directly in our app where a chip fails and debug it collaboratively. Right now, you need to check a lot of different testing tools and simulators—we’ll bring all of that in one place. 

The tedious part is going from a test failing to figuring out why that’s the case. Oftentimes, engineers need to rerun a test to see what the issue is—we can do that automatically. You don’t have to copy log files yourself anymore; we allow people to tag each other on suspicious test results and see what others have commented on, e.g., when a signal turned out to be high when it should be low. 

We’re also seeing a lot more interest in chiplets, people going from large, monolithic systems-on-chip to modularizing chips into components called chiplets. That’s also a good tailwind for what we’re doing. You can test smaller chips with open-source tools, but testing the entire system with all the chiplets is tricky, and that’s where we can make a difference. 

Another interesting trend is 3D chips. We haven’t gotten there yet; apart from memory, chips today have just one compute layer and are thus flat. But as they get more energy efficient, in the future we’ll be able to stack compute layers on top of each other. Existing verification tools will need to get a lot better to verify 3D chip designs. Multithreaded simulators will need to emerge, and verification engineers will need to upskill to deal with these much more challenging 3D designs.

The thing is, not many people dream about becoming a verification engineer, so there are already far too few engineers in the US today. So, everything we can do to increase productivity, such as testing methodology and writing tests automatically, will help a lot. AI will play a central role in writing code for test cases and combining tests efficiently to tease out bugs in chips. Being 98% sure that a microchip works is simply not good enough, so we’ll need a lot of testing. And our platform will help people to move from writing tests manually to writing and running all these tests automatically and keeping track of them.

Going forward, we want to integrate the three main simulators into our platform so that engineers can keep their existing workflows that already work for them. At the same time, we can help onboard startups to a new simulator. We’re developing more features for collaboration, test management and coverage, and views of which tests have failed. 

How Did You Evaluate Your Startup Idea?

Today, there are about 100,000 people in chip design and verification, and per-set licenses can typically run in the five-figure range. This short pen-and-paper calculation shows that there’s a multi-billion dollar market that we can address. Also, if we succeed in improving chip design verification, we help de-risk future chip companies, so we’re building a huge market behind us. 

There’s huge interest in custom silicon right now, eating into the market share of CPUs and, eventually, GPUs. And collaboration is a big deal, as it makes people so much more productive. We truly believe our platform will make chip designers more productive and enable them to generate more and better processor IPs. 

What Advice Would You Give Fellow Deep Tech Founders?

Listen to people whose opinions matter. That’s primarily your customers and then coworkers, cofounders, and employees. Next come friends in the industry, your family, and way below everyone else are other people who don’t have as much context about what you’re doing, such as other investors. There are not many people and startups in the design verification space or EDA in general, so if you’re working in such a space, you generally know more than most people anyway. 

Also, work with great people, as you’re more productive if you’re surrounded by smart people you respect. It’s like in Aristophanes’ speech in Plato’s Symposium: Bringing people’s talents together makes something far greater than the sum of their parts. Combined, they can challenge the gods.

Finally, two additional pieces of advice: Read great books, not just business books but great works of literature and philosophy, to avoid becoming too single-minded. Learn a new language every 5-10 years, as formulating your thoughts in another language helps you understand how you think. Expanding your mind is great, and it prevents you from becoming too intellectually vulnerable and sclerotic. 

Want to Learn More?

Check out SiLogy’s launch on Hacker News* to learn about what they’re doing


*Sponsored link—we greatly appreciate the support by SiLogy 

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